Synthesizing "+": Part One

In this tip, we're going to look at the synthesis of arithmetic circuitry. Suppose that the following circuit is to be realised using VHDL. You might decide to write the VHDL code like this...

architecture synth of arithmetic is
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all; -- this package allows Signed/Unsigned arithmetic
signal  a, b : std_logic_vector (7 downto 0);
signal  c : std_logic;
begin
variable s : Unsigned (7 downto 0);
begin
if (a > b) then
s := s + 1;
end if;
if (c = '1') then
s := s + 1;
end if;
...
end process;
end synth;

Functionally this code is correct. Unfortunately, some synthesis tools will not give you the hardware architecture you are looking for. For example, one of the golden rules of RTL synthesis is:

• if statements synthesise to multiplexers

So the architecture created by the synthesis tool is as follows: ... and there's no way to optimize the multiplexers away, or to merge the adders into the multiplexers as random logic with good results. Hmmm...

How do we write the code to create the multiplexer-less architecture we desire? The simple solution is to write the VHDL code without using if statements, as follows:

use work.std_boolean.all; -- ">" overloaded to return std_logic
variable compare : std_logic;
variable c2 : Unsigned (1 downto 0);
variable s : Unsigned (7 downto 0);
begin
compare := a > b;
c2 := Unsigned'('0' & c) + Unsigned'('0' & compare);
s := s + c2;
...
end process;

Note that this has required the use of a std_logic_vector comparison operator which is overloaded to return a std_logic type rather than the conventional boolean type. In this case, it is the ">" operator which is overloaded.

So to create the desired architecture, code up the VHDL without using IF statements. That's a tip!

Now, at the start of this Tip, I said “some” synthesis tools follow the rules of RTL synthesis to the letter to give a multiplexer-oriented structure - what about those that don't? Hmmm, sounds like the next Tip to me...