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Writing Structured Testbenches in VHDL

Wednesday October 27 2021

1 hour session (All Time Zones)
Presenter: Brian Jensen

Doulos Certified Training Instructor

Asia and Europe

Wednesday, October 27, 2021

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Wednesday, October 27, 2021

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

Webinar Overview:

Digital designers have been talking about design reuse for 30 years or so. Given that writing the testbench can be as much, if not more, effort than creating the design, testbench reuse is just as important, if not more. A structured testbench enables a powerful testbench to be designed that can much more easily be reused across block- and chip-level testing, across projects and across products.

This webinar introduces some modern verification concepts and shows how you can create a structured testbench in VHDL by presenting a VHDL testbench methodology.


  • Structured Testbench Overview
  • Stimulus Generation and BFMs
  • Checkers and Scoreboards
  • Random Stimulus and Functional Coverage
  • Other Testbench Features

Coding examples are shown running on Synopsys VCS and you can try out the examples yourself after the webinar on the free online simulation environment EDA Playground.

Brian Jensen

Brian Jensen - Doulos Certified Training Instructor - will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

If you have any queries, please contact [email protected]

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