This site contains VHDL source code written by Doulos staff. You are welcome to use the source code we provide but you must keep the copyright notice with the code. If you modify our code for your own requirements, it would be polite to acknowledge Doulos as the source of the original code in your own code with a VHDL comment to that effect. For example:
-- Original VHDL source code Copyright 1995-2021 DOULOS -- Modified by: your name here
When using our code as the starting point or inspiration for your own code developments, or when you substantially alter our code so that it no longer reflects the functionality or structure of our original code, you do not need an acknowledgement comment to Doulos in your VHDL code. However, we would be more than happy to have you e-mail us your code for inclusion in our Tip of the Month or Model of the Month pages. Naturally, full accreditation will be given to you.
Any mention of specific organizations or their products does not imply an endorsement by Doulos of either the organisation or the product.
Verilog is a registered trademark of Cadence Design Systems.
Synopsys is a registered trademark of Synopsys Inc.
Copyright 1995-2021 Doulos