KnowHow
Free Technical Resources

You will find Easier UVM here

At Last, One Functional Verification Methodology for Everyone!

Updated for UVM 1.2

UVM 1.0 was released on 28 Feb 2011 with the explicit endorsement of all the major simulator vendors. Since that time UVM has become the only show in town when it comes to standardized SystemVerilog verification methodologies. UVM has undergone a series of minor releases, which have fixed bugs and introduced new features.

The source code for the original 1.0 release, known as the UVM Base Class Library (BCL), evolved from the UVM Early Adopter release, which in turn was based on OVM version 2.1.1. The most obvious difference between OVM and UVM-EA was that all occurrence of the prefix "ovm_" were quite literally replaced with "uvm_", "OVM_" by "UVM_", "tlm_" by "uvm_tlm_", and so forth. The UVM-EA kit included a script to convert existing OVM source code. UVM-EA added a few new features on top of OVM 2.1.1, which itself added a few new features to OVM 2.0. The most noticeable additions in the 1.0 release were:

• An end-of-test objection mechanism to ease the task of cleaning up at the end of a verification run
• A callback mechanism that provides an alternative to the factory for customizing behavior
• A report catcher to ease the task of customized report handling
• A heartbeat mechanisms to monitor the liveness of verification components.

The UVM 1.0x releases add the following features to the Early Adopter release

• Register layer, based on the Register Abstraction Layer of VMM
• Phasing extensions, meaning a subdivided run phase, user-defined phases, and user-defined relationships between phases
• Sequence mechanism cleaned up, with the old sequence and sequencer macros deprecated
• TLM-2.0 interfaces, based on the SystemC TLM-2.0 standard
• Resource database, improving on the old set_config interface
• End-of-test mechanism cleaned up
• Command line processor, to give access to command line arguments

UVM 1.2 was released in June 2014 and has completed a period of public review. UVM 1.2 is somewhat controversial in that the experts disagree as to whether some of the new features introduced in UVM 1.2 represent a step forward or a step backward. The most conservative advice right now would be to wait-and-see. You do not need to adopt any of the features introduced in UVM-1.2 immediately, and it may be wiser to see how things shake down.

Click here for a Summary of Changes in UVM 1.2

UVM 1.2 includes some bug fixes and some improvements to the documentation, which are welcome changes, of course. There are two specific features of UVM 1.2 that you might like to know about right away. The starting_phase variable has been deprecated and replaced with two methods set_starting_phase and get_starting_phase, so you might like to start using these methods. Also, there is a new method uvm_objection::set_propagate_mode that can be used to switch off the hierarchical propagation of objections and thus speed up simulation in some circumstances. (The propagation of objections is usually redundant anyway.)

 

• Download UVM from Accellera
• Visit the UVM community webpage

Note: Registration many be required to access some of these resources (See Privacy Policy). There are also some tutorials below.

 

• UVM Verification Primer - an introductory tutorial on UVM.
• From OVM to UVM: Getting Started with UVM - a first example
• Easier UVM - a tutorial for VHDL and Verilog Users
• Easier UVM for Functional Verification by Mainstream Users - the paper and recording as presented at DVCon 2011
• Easier UVM - Events
• Easier SystemVerilog with UVM: Taming the Beast - the paper presented at DVCon 2012
• A Beginner's Guide to Using SystemC TLM-2.0 IP with UVM - the paper presented at SNUG UK, Germany and France 2012
• UVM: Now or Never? - the reasons you should (or should not) be adopting UVM right now
• First Steps with UVM - Download
• First Steps with UVM: Part 1 - a simple, complete UVM source code example
• First Steps with UVM: Part 2 - showing how to drive pins on the design-under-test
• First Steps with UVM: Part 3 - showing how to use a sequencer to generate transactions
• How Much SystemVerilog Training Do You Need? - explains how to choose the right training
• Easier UVM - Coding Guidelines and Code Generation - the paper presented at DVCon 2014
• UVM Objections - code example download (As seen at SNUG 2015 Silicon Valley)
• Run-Time Phasing in UVM: Ready for the Big Time or Dead in the Water - the paper presented at DVCon 2015
• Aliasing UVM Registers
• Introducing Easier UVM - introduction to the Coding Guidelines and Code Generator
• Easier UVM - The Big Picture - the overall structure of a UVM verification environment
• Key Concepts of the Easier UVM Code Generator - things you need to know before you start
• Easier UVM - Components and Phases
• Easier UVM - Configuration
• TLM Connections in UVM
• Running Easier UVM in EDA Playground
• Creating aliased registers by using register callbacks.

The UVM Golden Reference Guide was published at DAC 48 in June 2011.

You can find out more about it and purchase the guide on-line in the Doulos Web Shop. There is also a Kindle version available from Amazon.

Easier UVM Coding Guidelines

• Introduction to the Easier UVM Coding Guidelines
• Summary of the Easier UVM Coding Guidelines
• Detailed Explanation of the Easier UVM Coding Guidelines
• Easier UVM Glossary
• Easier UVM Coding Guidelines - Download

 

Easier UVM - Deeper Explanations

• Coverage-Driven Verification Methodology
• Requests, Responses, Layered Protocols and Layered Agents
• How to Access a Parameterized SystemVerilog Interface from UVM

 

Easier UVM Code Generator

• Easier UVM Coding Guidelines - Download
• Easier UVM Code Generator - Tutorial Part 1: Getting Started
• Easier UVM Code Generator - Tutorial Part 2: Adding User-Defined Code
• Easier UVM Code Generator - Tutorial Part 3: Adding the Register Layer
• Easier UVM Code Generator - Tutorial Part 4: Hierarchical Verification Environments
• Easier UVM Code Generator - Tutorial Part 5: Split Transactors
• Easier UVM Code Generator - Frequently Asked Questions (FAQ)
• Easier UVM Code Generator - Reference Guide

 

Easier UVM Video Tutorial

• Introducing Easier UVM
• Easier UVM - The Big Picture
• Key Concepts of the Easier UVM Code Generator
• Running Easier UVM in EDA Playground
• Easier UVM - Components and Phases
• Easier UVM - Configuration
• TLM Connections in UVM
• Easier UVM - Transaction Classes
• Easier UVM - Sequences
• Easier UVM - Tests
• Easier UVM - Reporting
• Easier UVM - Register Layer
• Easier UVM - Parameterized Interfaces
• Easier UVM - Scoreboards
• The Finer Points of UVM Sequences (Recorded Webinar)
• UVM Run-Time Phasing (Recorded Webinar)
• A YouTube playlist with all the above videos and more

 

Easier UVM Paper and Poster

• Easier UVM - Coding Guidelines and Code Generation - as presented at DVCon 2014

 

Easier UVM Q&A Forum

• Easier UVM Google Group

 

Easier UVM Examples Ready-to-Run on EDA Playground

• Minimal example with driver
• Minimal example with coverage in a subscriber as well as driver and monitor.
• Minimal example with register sequence and register block
• Example with four interfaces/agents, two of which use a register model.
• Minimal example with dual-top modules and split transactors
• Minimal example showing a UVM sequence getting information from the config database
• Minimal example showing features of objections and the command line processor
• Minimal example showing the reporting features of UVM.
• Example that drops an objection when coverage exceeds some threshold
• Example that sends a response transaction from the driver back to the uvm_reg_adapter
• Example that uses a frontdoor sequence to pass a response object back to the register sequence that called read/write
• Example of a parameterized interface generated from an Easier UVM interface template file
• Example that pulls in a user-defined parameterized interface
• Example of a reference model with the Syosil scoreboard

 

Back to the full list of UVM Resources