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Synthesis of SystemVerilog RTL Constructs

Friday July 23 2021

1 hour session (All Time Zones)
Presenter: Brian Jensen

Doulos Certified Training Instructor

Asia and Europe

Friday, July 23, 2021

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Americas

Friday, July 23, 2021

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)


Webinar Overview:

SystemVerilog offers many new register-transfer level constructs, allowing for more concise RTL coding as well as the specification of design intent for simulation, synthesis and formal verification.

This webinar will help you understand the new synthesizable RTL constructs including the three new types of always blocks, priority, unique, wild equality, case inside, inside operator and streaming operators.

You can expect to learn about:

  •  How to use the RTL constructs for more concise RTL coding
  •  Specify design intent
  •  Examine the simulation and synthesis results

Practical examples will be provided using Synopsys VCS® in the online simulation environment EDA Playground.


Brian Jensen

Brian Jensen - Doulos Certified Training Instructor - will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.


Attendance is free of charge

If you have any queries, please contact [email protected]


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SystemVerilog training available from Doulos:

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